This application relates to articles and methods for chemical-mechanical polishing. In particular, the invention relates to a chemical-mechanical polishing pad for precisely and rapidly polishing a surface of a semiconductor wafer or the like.
In recent years, chemical-mechanical polishing (CMP) has become the technology of choice among semiconductor chip fabricators to planarize the surface of semiconductor chips as circuit pattern layers are laid down. CMP technology is well known, and is typically accomplished using a polishing pad and a polishing composition.
The fabrication of semiconductor wafers typically involves the formation of a plurality of integrated circuits on a semiconductor substrate of, for example, silicon, gallium arsenide, indium phosphide, or the like. The integrated circuits are generally formed by a series of process steps in which patterned layers of materials, such as conductive, insulating, and semiconducting materials, are formed on the substrate. In order to maximize the density of integrated circuits per wafer, an extremely planar, precision-polished substrate is needed at various stages throughout the semiconductor wafer production process. As such, semiconductor wafer production typically involves the use of at least one, and more typically more than one polishing step.
The polishing steps typically involve rotating or rubbing a polishing pad and semiconductor wafer substrate against each other in the presence of a polishing fluid or composition, usually using a controlled and repetitive motion. The pad aids in mechanical polishing of the semiconductor substrate, while the polishing fluid aids in both mechanical and chemical polishing of the substrate and facilitates the removal and transport of abraded material off of and away from the rough surface of the article. Typically, a polishing fluid is interposed between the rough surface of the article that is to be polished and the work surface of the polishing pad. The polishing fluid is often alkaline and may contain an abrasive material, e.g., particulate cerium oxide or silica, among others. Polishing can be used to remove either metals, dielectrics, or other materials in the electronics industry.
Various CMP pads of different materials have been described or are in current use, for example a metal pad described in U.S. Pat. No. 6,022,268; a polishing pad containing particles as described in U.S. Pat. No. 5,489,233; a polishing pad of polymer-impregnated woven fiber sold under the trade name POLITEX; and a pad of a polymer sheet containing void spaces formed by in situ production or incorporation of hollow fill materials (sold under the trademark IC 1000). A composite pad of multiple layers of materials having an outer substrate that contacts the surface of the semiconductor being polished is included among pads in current use. CMP pads made from porous foamed materials are also known. For example, U.S. Pat. No. 6,913,517 describes a microporous polyurethane polishing pad, and U.S. Pat. No. 4,954,141 describes polishing pads made of a foamed fluorine-containing polymer. U.S. Pat. No. 7,059,936 describes a polishing pad having a low surface energy, particularly for use with a hydrophobic polishing composition.
Despite intensive development directed to CMP pads, there remains a continuing perceived need in the art for continual improvement of polishing efficiency and effectiveness, in particular characterized by low defects. With CMP pads, there is often a trade-off between rate of removal, when polishing material away, and defect level in the polished wafer. In other words, a harder pad can result in faster polishing, which in turn can result in higher defects. It would be desirable to obtain a CMP pad that polishes fast, is highly efficient, and yet results in a low defect level.
Further, when using a highly active polishing composition for polishing a semiconductor wafer, the chemical properties and mechanical structure of the CMP pad can deteriorate. As a result, the efficiency of the polishing pad can decrease, for example, the polishing rate can be reduced, and increased surface roughness, undulations, and/or damage can result. Frequent replacement of an expensive polishing pad by a costly new pad is undesirable. Furthermore, even when a pad deteriorates only slightly over time, the conditions of polishing such as working pressure, rotation speed of a polishing plate, and temperature and flow rate of cooling water for the polishing plate can require continuous control to cope with the degree of deterioration, in order to obtain the desired polishing of a surface of a semiconductor wafer. It would be desirable to obtain a CMP pad that has improved resistance to deterioration after repeated polishing of wafers.
Thus, there remains a continuing need in the art for improved CMP pads, particularly pads that provide polished surfaces with low defects. It would be a further advantage for such pads to have good resistance to deterioration, as well as good polishing efficiency, workability, and low cost. It would still further be desirable to more finely control or tailor the abrasive properties of the polishing pad to balance its ability to remove a particular coating without attacking a particular surface material or cause unwanted scratching or other damage. It would also be desirable to be able to economically manufacture and customize such pads for a particular application.